Memory benchmark on UltraSPARC T2

Phil ran a memory benchmark and summarized his results in Niagara 2 memory throughput according to libMicro:

[...] seeing 240ns latency, which equates to a throughput of 267 million memory reads per second (i.e. 64 / 0.240e-6). Just to set this in context, here are some data for a quad socket Tigerton system running at 2.93GHz...
[...] his shows a peak throughput of about 86 million memory reads per second (i.e. 16 / 0.186e-6), making the single chip UltraSPARC T2 processor's throughput 3x that of its quad chip rival.

It´s a micro benchmark, but it´s a part of the puzzle why an UltraSPARC T2 is able to outperform a processor with almost 2.5 times more clock cycles per seond.